1. Field of the Invention
The present invention relates to an integrated circuit having a PLL that generates an internal clock signal and to a PLL jitter measuring method thereof.
2. Description of the Related Art
In recent years, integrated circuits have been increasingly used for data transmission systems. As an example of data transmission systems, a so-called Rambus system that bidirectionally transmits data between a master device and a slave device is known.
In the Rambus system, data is transmitted from a master device to a slave device in synchronization with a transmission clock signal (that is referred to as cfm (clock from master) signal). The slave device receives the transmission data from the master device in synchronization with the transmission clock cfm signal. On the other hand, data is transmitted from the slave device to the master device in synchronization with a transmission clock signal (that is referred to as ctm (clock to master) signal). The master device receives the transmission signal from the slave device in synchronization with the transmission clock ctm signal.
Each of the master device and the slave device used in the Rambus system should internally generate the transmission clock signal and the reception clock signal that synchronizes with the transmission clock signal. Thus, each of the master device and the slave device has a PLL that generates the transmission clock signal and another PLL that generates the reception clock signal and that is a phase locked loop which is asynchronized with the transmission clock signal of the master device or the slave device.
On the other hand, in the data transmission systems such as the Rambus system, the transmission clock signal and the reception clock signal should be prevented from being affected by clock skews due to jitters. In particular, when the frequencies of the transmission clock signal and the reception clock signals are high, the influences of the jitters to these clock signals should be monitored and prevented so that the relevant integrated circuit can be normally operated.
In the master device and the slave device used in the Rambus system, the jitter of the transmission clock signal generated by the PLL is indirectly measured by monitoring and testing the transmission data that is output from each device to the outside.
However, the jitter of the reception clock signal generated in each device is not output to the outside thereof. Thus, this jitter cannot be measured from the outside of the device.
Consequently, as a conventional jitter measuring method, the package of the integrated circuit of each device is removed. A measurement probe is directly contacted to the PLL that generates the reception clock signal. The output signal of the PLL is observed with an oscilloscope so as to measure the jitter of the reception clock signal.
However, in the conventional method, to measure the jitter of the PLL that generates the reception clock signal, the package of the integrated circuit should be removed. Thus, it is impossible to measure jitters of all integrated circuits to be tested.
On the other hand, in Japanese Patent Laid-Open Publication No. 8-62298, a semiconductor integrated circuit testing method is disclosed. In this method, data that is input to a high speed interface portion is looped as output data back to the high speed interface portion. The output data is tested by an LSI tester.
However, this related art reference teaches only the loopback of input data to the outside. However, it teaches neither a reception clock signal generated in an integrated circuit, nor the measurement of a jitter of a reception clock signal.